The present invention relates to a memory cell having a trench capacitor and a method for fabricating it. The trench capacitor is arranged in a substrate and, e.g. in a DRAM (dynamic random access memory), together with a selection transistor may form a DRAM memory cell.
Memory devices such as, for example, DRAMs comprise a cell array and a driving periphery. Individual memory cells are arranged in the cell array.
A DRAM chip contains a matrix of memory cells which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by the activation of suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor comprises, inter alia, two diffusion regions which are isolated from one another by a channel controlled by a gate. Depending on the direction of current flow, one diffusion region is designated as the drain region and the other is designated as the source region.
One of the diffusion regions is connected to a bit line, the other is connected to a capacitor and the gate is connected to a word line. Through the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the diffusion regions through the channel is switched on and off.
The progressive miniaturization of memory devices increases the integration level step by step. The increase in the integration level means that the substrate surface available per memory cell decreases more and more.
In order to effectively utilize the available area, it is possible to form the selection transistor as a vertical transistor in a trench above a trench capacitor. A generic memory cell having a trench capacitor and a vertical transistor is described in U.S. Pat. No. 5,177,576. Further embodiments for trench capacitors or transistors are described in U.S. Pat. Nos. 5,208,657 and 5,744,386.
In those embodiments, there is the problem of connecting the gate of the vertical transistor to a word line and of connecting the drain contact of the vertical transistor to a bit line. With progressive miniaturization, the requirements made of these two connections with regard to alignment accuracy will become more stringent. There is an additional problem in the formation of an isolation trench (STI), which should neither be formed too near the trench of the trench capacitor, since the functioning of the vertical transistor arranged in the upper region of the trench is impaired in this case, nor should the isolation trench (STI) be too far removed from the trench of the trench capacitor, since this would waste valuable substrate surface.
The object of the present invention is to provide a memory cell which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which is improved with regard to its integration capability and which has a trench for use with a transistor. It is a further object of the invention to provide a corresponding fabrication method.
With the above and other objects in view there is provided, in accordance with the invention, a memory cell, comprising:
a substrate having a trench formed therein with a lower region, an upper region, and a trench opening;
a trench capacitor formed in the trench;
a conductive trench filling forming a constituent part of the trench capacitor in the lower region of the trench;
a vertical selection transistor formed at the upper region of the trench, the vertical selection transistor having a lower doping region disposed in the substrate beside the upper region of the trench, an upper doping region disposed above the lower doping region in the substrate at the upper region of the trench, and a gate electrode; and
a dielectric layer disposed above the trench and projecting laterally beyond the trench opening, the dielectric layer having an inner opening formed therein extending completely through the dielectric layer.
In other words, a vertical transistor is formed by the lower doping region, arranged laterally beside the trench, the upper doping region and the channel region situated in between. The junction depth (the thickness of the source and drain regions is usually referred to as junction depth in field-effect transistors) of the upper and lower doping regions and the thickness of the channel region are determined e.g. by the distance from an isolation trench. The arrangement of the dielectric layer with its inner opening renders the trench and thus the trench filling uncovered through the inner opening accessible for contact-connections. By way of example, a gate electrode of the vertical transistor may be connected here. By virtue of the invention""s arrangement of the dielectric layer projecting beyond the trench opening, the dielectric layer can be used as an etching mask e.g. during the etching of an isolation trench. This procedure has the advantage that the junction depth of the vertical transistor is not defined by a lithography step, but rather can be carried out in a self-aligned manner with respect to the trench with the aid of the dielectric layer.
In accordance with an added feature of the invention, the dielectric layer is recessed into the substrate. Recessing the dielectric layer into the substrate has the advantage that there is a small topology for subsequent layers on the substrate surface. The conformity and uniformity of subsequent layers are thereby improved. In addition, a planar surface is better suited to subsequent photolithographic exposure steps, since the depth of focus in this case only has to encompass a relatively small region.
In accordance with an additional feature of the invention, the dielectric layer has an upper edge and the substrate has a substrate surface and the upper edge of the dielectric layer is arranged at the same level as the substrate surface. The arrangement at the same level avoids a topography step. This configuration can be fabricated e.g. by means of a CMP step (chemical mechanical polishing).
In accordance with an advantageous further feature of the invention, an isolation trench filled with an insulator is arranged beside the dielectric layer. The isolation trench (STI) has the task of insulating adjacent memory cells from one another. It is particularly advantageous here that the dielectric layer can be used as an etching mask for the etching of the isolation trench. This enables self-aligned formation of the isolation trench, the position of the isolation trench being defined not by the lithographic accuracy that can be achieved, but by the position of the dielectric layer.
In accordance with again a further advantageous feature of the invention, a doped region is arranged beside the dielectric layer in the substrate. The doped region beside the dielectric layer is connected to a bit line which runs on the doped region. In addition, the doped region is connected to the upper doping region. This enables a compact arrangement of the memory cells which has an advantageously small connection resistance to the bit line and an advantageously small bit line capacitance.
In accordance with another feature of the invention, a gate electrode is arranged below the dielectric layer. In this case, the gate electrode has the task, for example, of controlling the selection transistor of the memory cell. In this case, the gate electrode is advantageously arranged below the dielectric layer, with the result that it can be connected through the inner opening in the dielectric layer to a word line by means of a word line contact.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating a memory cell, which comprises the following method steps:
etching a trench in the substrate through a first mask formed on the substrate;
forming a trench capacitor in the trench;
forming a vertical selection transistor with a gate electrode in the trench;
widening the first mask and thereby uncovering a widened portion having a larger cross section than a cross section of the trench;
recessing the substrate and the gate electrode, formed in the trench, in the region uncovered by the widened portion, a recess being formed; and
forming a dielectric layer in the recess.
In the method according to the invention, the mask which is used for etching the trench for the trench capacitor is widened and used for etching a recess. The widening of the mask has the advantage that a self-aligned process is involved which does not require further photolithographic steps but rather forms a recess in a self-aligned manner around the already existing trench.
In one method step, dopant is introduced into the gate electrode and the substrate into the region of the recess. This process step advantageously forms an upper doping region in the substrate, which can be used as source or drain region of a vertical transistor and can be connected to a bit line.
A further method step provides for a dielectric layer to be deposited in the recess and lateral edge webs to be formed from the dielectric layer by means of an anisotropic etching process. This method step forms the dielectric layer in a self-aligned manner in the recess, the dielectric layer having an inner opening and thus being similar to the form of a torus. This has the advantage that a further lithography step, which would comprise alignment inaccuracies, can be avoided.
A further method step provides for a second mask to be arranged on the substrate and patterned, and for the substrate to be uncovered in a region in which the second mask is patterned. By means of this procedure, the first mask is patterned in a region in which an isolation trench can subsequently be formed. In this case, the removal of the first mask e.g. uncovers a region of the substrate surface and a region of the dielectric layer.
In accordance with a concomitant feature of the invention, the first mask, the second mask and the lateral edge webs form a common etching mask during the etching of an isolation trench. As a result, the isolation trench is etched into the uncovered substrate surface, the alignment accuracy of the photolithography of the second mask not specifying the positioning accuracy of the isolation trench, rather the isolation trench being spaced apart from the trench of the trench capacitor by the dielectric layer in a self-aligned manner, and thus having a distancexe2x80x94which can be set very accuratelyxe2x80x94from the diffusion regions introduced into the substrate. This enables the junction depth to be set very accurately.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell having a trench capacitor and method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.